library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity aluCmp is
  
  port (
    A        : in  std_logic_vector(31 downto 0);
    B        : in  std_logic_vector(31 downto 0);
    uns    : in  std_logic;
    lessthan : out std_logic);  

end aluCmp;

architecture arch of aluCmp is
  
  component adder33
    port (
      Cin      : in  std_logic;
      A        : in  std_logic_vector(32 downto 0);
      B        : in  std_logic_vector(32 downto 0);
      Sum      : out std_logic_vector(32 downto 0);
      Overflow : out std_logic);
  end component;

  signal S   : std_logic_vector(32 downto 0);
  signal A_t   : std_logic_vector(32 downto 0);
  signal B_t   : std_logic_vector(32 downto 0);  
  
  signal Cin : std_logic;
  signal ov  : std_logic;
begin  -- arch

  Cin <= '1';

  A_t <= ((not uns) and A(31)) & A;
  B_t <= ((not uns) and B(31)) & B;

  
  add_c : adder33 port map (
    Cin => Cin, A => A_t, B => B_t, Sum => S, overflow => ov);

  lessthan <= S(32) or ( A_t(32) and not B_t(32));
  
end arch;
